Chapter 4 Code
To comply the Chapter 4 Verilog codes within the book titled Fundamental Digital Circuits and FPGA
Last updated
To comply the Chapter 4 Verilog codes within the book titled Fundamental Digital Circuits and FPGA
Last updated
/*---------------------------------------------------------------------------------------------------
*- File name: sn74hc08.v
*- Top Module name: sn74hc08
- Submodules: N/A
*- Description: Implement the logic functions of a Quad 2-input AND gate
*-
*- Example of Usage:
You can assign the input and output pins of this module to the GPIOs of the STEPFPGA board
To observe the logic behavior, you may need additional components such as swiches, pushbuottons
LEDs, resistors...and build the circuit on a breadboard or other medias.
- Reliability:
This code is intended for educational and demonstration purposes and has not been
validated for use in production systems. Users are advised to thoroughly test the
module in their specific application context.
- Copyright: Copyright (c) 2023 by EIM Technology
- License: MIT License
--------------------------------------------------------------------------------------------------- */
module sn74hc08 (pin1,pin2,pin3,pin4,pin5,pin6,pin7,pin8,
pin9,pin10,pin11,pin12,pin13,pin14);
input pin1,pin2,pin4,pin5,pin9,pin10,pin12,pin13;
output pin3,pin6,pin8,pin11;
output pin7,pin14; // connects to Vcc and GND
wire A1,B1,Y1,A2,B2,Y2,A3,B3,Y3,A4,B4,Y4;
assign A1 = pin1;
assign B1 = pin2;
assign A2 = pin4;
assign B2 = pin5;
assign A3 = pin9;
assign B3 = pin10;
assign A4 = pin12;
assign B4 = pin13;
assign pin3 = Y1;
assign pin6 = Y2;
assign pin8 = Y3;
assign pin11 = Y4;
assign pin7 = 1'b0;
assign pin14 = 1'b1;
assign Y1 = A1 & B1;
assign Y2 = A2 & B2;
assign Y3 = A3 & B3;
assign Y4 = A4 & B4;
endmodule
/*---------------------------------------------------------------------------------------------------
*- File name: sn74hc283.v
*- Top Module name: sn74hc283
- Submodules: N/A
*- Description: Implement the logic functions of a 4-bit Binary Full Adder
*-
*- Example of Usage:
You can assign the input and output pins of this module to the GPIOs of the STEPFPGA board
To observe the logic behavior, you may need additional components such as swiches, pushbuottons
LEDs, resistors...and build the circuit on a breadboard or other medias.
- Reliability:
This code is intended for educational and demonstration purposes and has not been
validated for use in production systems. Users are advised to thoroughly test the
module in their specific application context.
- Copyright: Copyright (c) 2023 by EIM Technology
- License: MIT License
--------------------------------------------------------------------------------------------------- */
module sn74hcf283 (pin1,pin2,pin3,pin4,pin5,pin6,pin7,pin8,
pin9,pin10,pin11,pin12,pin13,pin14,pin15,pin16);
input pin5,pin3,pin14,pin12,pin6,pin2,pin15,pin11; // two 4-bit Addends
input pin7; // Initial Carry input
output pin9; // Final Carry output
output pin8,pin16; // Connect to VCC and GND
output pin4,pin1,pin13,pin10; // 4-bit output Sum
wire [3:0] a,b,sum;
wire ci,co;
assign pin8 = 1'b0;
assign pin16 = 1'b1;
assign a[0] = pin5;
assign a[1] = pin3;
assign a[2] = pin14;
assign a[3] = pin12;
assign b[0] = pin6;
assign b[1] = pin2;
assign b[2] = pin15;
assign b[3] = pin11;
assign ci = pin7;
assign pin9 = co;
assign pin4 = sum[0];
assign pin1 = sum[1];
assign pin13 = sum[2];
assign pin10 = sum[3];
assign {co,sum} = a + b + ci;
endmodule/*---------------------------------------------------------------------------------------------------
*- File name: sn74hc138.v
*- Top Module name: sn74hc138
- Submodules: N/A
*- Description: Implement the logic functions of a 3-to-8 Line Decoder/Demultiplexer with Inverting Output
*-
*- Example of Usage:
You can assign the input and output pins of this module to the GPIOs of the STEPFPGA board
To observe the logic behavior, you may need additional components such as swiches, pushbuottons
LEDs, resistors...and build the circuit on a breadboard or other medias.
- Reliability:
This code is intended for educational and demonstration purposes and has not been
validated for use in production systems. Users are advised to thoroughly test the
module in their specific application context.
- Copyright: Copyright (c) 2023 by EIM Technology
- License: MIT License
--------------------------------------------------------------------------------------------------- */
module sn74hc138 (pin1,pin2,pin3,pin4,pin5,pin6,pin7,pin8,
pin9,pin10,pin11,pin12,pin13,pin14,pin15,pin16);
input pin1,pin2,pin3; // 3 inputs corresponding to the address location
input pin4,pin5,pin6; // 3 inputs for Enable
output pin7,pin9,pin10,pin11,pin12,pin13,pin14,pin15;
output pin8,pin16; // connects to VCC and GND
// ***** intermediate signals *****
wire [2:0] a ;
reg [7:0] q ;
wire sel;
assign pin8 = 1'b0;
assign pin16 = 1'b1;
assign a = {pin3,pin2,pin1};
assign sel = (~pin4)&(~pin5)& pin6;
assign pin7 = q[7];
assign pin9 = q[6];
assign pin10 = q[5];
assign pin11 = q[4];
assign pin12 = q[3];
assign pin13 = q[2];
assign pin14 = q[1];
assign pin15 = q[0];
always@(a,sel) begin
if(!sel)
q = 8'b1111_1111;
else begin
case(a)
3'b000: q = 8'b1111_1110;
3'b001: q = 8'b1111_1101;
3'b000: q = 8'b1111_1011;
3'b000: q = 8'b1111_0111;
3'b000: q = 8'b1110_1111;
3'b000: q = 8'b1101_1111;
3'b000: q = 8'b1011_1111;
3'b000: q = 8'b0111_1111;
default:q = 8'b1111_1111;
endcase
end
end
endmodule/*---------------------------------------------------------------------------------------------------
*- File name: sn74hc74.v
*- Top Module name: sn74hc74
- Submodules: N/A
*- Description: Implement the logic functions of a Dual Positive Edge Triggered D-Flipflop
*-
*- Example of Usage:
You can assign the input and output pins of this module to the GPIOs of the STEPFPGA board
To observe the logic behavior, you may need additional components such as swiches, pushbuottons
LEDs, resistors...and build the circuit on a breadboard or other medias.
- Reliability:
This code is intended for educational and demonstration purposes and has not been
validated for use in production systems. Users are advised to thoroughly test the
module in their specific application context.
- Copyright: Copyright (c) 2023 by EIM Technology
- License: MIT License
--------------------------------------------------------------------------------------------------- */
module sn74hc74 (pin1,pin2,pin3,pin4,pin5,pin6,pin7,pin8,
pin9,pin10,pin11,pin12,pin13,pin14);
input pin3,pin11; // 2 inputs for CLOCK
input pin1,pin13; // 2 inputs for RESET
input pin4,pin10; // 2 inputs for SET
input pin2,pin12; // 2 inputs for DATA
output pin7,pin14; // Connects to VCC and GND
output pin5,pin6,pin8,pin9;
wire clk1,clk2,reset1_n,reset2_n,set1_n,set2_n,d1,d2;
reg [1:0] q1,q2;
assign pin7 = 1'b0;
assign pin14 = 1'b1;
assign clk1 = pin3;
assign clk2 = pin11;
assign reset1_n = pin1;
assign reset2_n = pin13;
assign set1_n = pin4;
assign set2_n = pin10;
assign d1 = pin2;
assign d2 = pin12;
assign pin5 = q1[1]; //1Q
assign pin6 = q1[0]; //1Q'
assign pin9 = q2[1]; //2Q
assign pin8 = q2[0]; //2Q'
//Building the first channel of D flipflop;
always @(negedge reset1_n or negedge set1_n or posedge clk1) begin
if(reset1_n==0)
q1<=2'b01;
else if(set1_n==0)
q1<=2'b10;
else
q1<={d1,~d1};
end
//Building the second channel of D flipflop
always@(negedge reset2_n or negedge set2_n or posedge clk2) begin
if(reset2_n==0)
q2<=2'b01;
else if(set2_n==0)
q2<=2'b10;
else
q2<={d2,~d2};
end
endmodule/*---------------------------------------------------------------------------------------------------
*- File name: sn74hc165.v
*- Top Module name: sn74hc165
- Submodules: N/A
*- Description: Implement the logic functions of an 8-bit Parallel-load Shift Registers
*-
*- Example of Usage:
You can assign the input and output pins of this module to the GPIOs of the STEPFPGA board
To observe the logic behavior, you may need additional components such as swiches, pushbuottons
LEDs, resistors...and build the circuit on a breadboard or other medias.
- Reliability:
This code is intended for educational and demonstration purposes and has not been
validated for use in production systems. Users are advised to thoroughly test the
module in their specific application context.
- Copyright: Copyright (c) 2023 by EIM Technology
- License: MIT License
--------------------------------------------------------------------------------------------------- */
module sn74hc165 (pin1,pin2,pin3,pin4,pin5,pin6,pin7,pin8,
pin9,pin10,pin11,pin12,pin13,pin14,pin15,pin16);
input pin3,pin4,pin5,pin6,pin11,pin12,pin13,pin14;
input pin2,pin15;
input pin1;
input pin10;
output pin8,pin16;
output pin7,pin9;
wire [7:0] data;
wire clk,load,sel;
reg [7:0] q;
assign pin8 = 1'b0;
assign pin16= 1'b1;
assign data[0]=pin11;
assign data[1]=pin12;
assign data[2]=pin13;
assign data[3]=pin14;
assign data[4]=pin3;
assign data[5]=pin4;
assign data[6]=pin5;
assign data[7]=pin6;
assign clk=pin2|pin15;
assign load=pin1;
assign pin9=q[7]; //Q
assign pin7=~q[7]; //~Q
assign sel=pin10;
always@(posedge clk or negedge load) begin
if(!load)
q<=data;
else
q<={q[6:0],sel};
end
endmodule/*---------------------------------------------------------------------------------------------------
*- File name: sn74hc393.v
*- Top Module name: sn74hc393
- Submodules: N/A
*- Description: Implement the logic functions of a Dual 4-Stage Binary Counter
*-
*- Example of Usage:
You can assign the input and output pins of this module to the GPIOs of the STEPFPGA board
To observe the logic behavior, you may need additional components such as swiches, pushbuottons
LEDs, resistors...and build the circuit on a breadboard or other medias.
- Reliability:
This code is intended for educational and demonstration purposes and has not been
validated for use in production systems. Users are advised to thoroughly test the
module in their specific application context.
- Copyright: Copyright (c) 2023 by EIM Technology
- License: MIT License
--------------------------------------------------------------------------------------------------- */
module sn74hc393 (pin1,pin2,pin3,pin4,pin5,pin6,pin7,pin8,
pin9,pin10,pin11,pin12,pin13,pin14);
input pin1,pin13; // two Clock signal
input pin2,pin12; // two Clear enable signal
output pin7,pin14; // Connects to VCC and GND
output pin3,pin4,pin5,pin6,pin11,pin10,pin9,pin8; // two 4-bit Binary counter output
wire clk1,clk2,clr1,clr2;
reg [3:0] count1,count2;
assign pin7 = 1'b0;
assign pin14 = 1'b1;
assign clk1 = pin1;
assign clk2 = pin13;
assign clr1 = pin2;
assign clr2 = pin12;
assign pin3 = count1[0];
assign pin4 = count1[1];
assign pin5 = count1[2];
assign pin6 = count1[3];
assign pin11 = count2[0];
assign pin10 = count2[1];
assign pin9 = count2[2];
assign pin8 = count2[3];
always@(negedge clk1 or posedge clr1)begin
if(clr1)
count1 <= 4'b0000;
else begin
if(count1 == 4'b1111)
count1 <= 4'b0000;
else
count1 <= count1 + 1'b1;
end
end
always@(negedge clk2 or posedge clr2)begin
if(clr2)
count2 <= 4'b0000;
else begin
if(count2 == 4'b1111)
count2 <= 4'b0000;
else
count2 <= count2 + 1'b1;
end
end
endmodule
